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VNW50N04A
"OMNIFET": FULLY AUTOPROTECTED POWER MOSFET
Table 1. General Features
Type VNW50N04A Vclamp 42 V RDS(on) 0.012 Ilim 50 A
Figure 1. Package

LINEAR CURRENT LIMITATION THERMAL SHUT DOWN SHORT CIRCUIT PROTECTION INTEGRATED CLAMP LOW CURRENT DRAWN FROM INPUT PIN DIAGNOSTIC FEEDBACK THROUGH INPUT PIN ESD PROTECTION DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) COMPATIBLE WITH STANDARD POWER MOSFET STANDARD TO-247 PACKAGE

DESCRIPTION The VNW50N04A, is a monolithic device made using STMicroelectronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. Fault feedback can be detected by monitoring the voltage at the input pin.
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Table 2. Order Codes
Package TO-247 Tube VNW50N04A Tape and Reel -
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REV. 2 June 2004 1/12
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Figure 2. Block Diagram
Table 3. Absolute Maximum Ratings
Symbol VDS Vin ID IR Vesd Ptot Tj Tc Tstg Parameter Drain-Source Voltage (Vin = 0) Input Voltage Drain Current Reverse DC Output Current
Electrostatic Discharge (C = 100 pF, R =1.5 K) Total Dissipation at Tc = 25 C
Operating Junction Temperature Case Operating Temperature Storage Temperature
Table 4. Thermal Data
Symbol
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Rthj-case Rthj-amb
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Value -100 2000 208
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Unit V V A A V W C C C
Internally Limited
Internally Limited Internally Limited -55 to 150
Parameter Max Max
Value 0.6 30
Unit C/W C/W
Thermal Resistance Junction-case Thermal Resistance Junction-ambient
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ELECTRICAL CHARACTERISTICS (Tcase = 25C unless otherwise specified) Table 5. Off
Symbol VCLAMP VCLTH VINCL IDSS IISS Parameter Drain-source Clamp Voltage Drain-source Clamp Threshold Voltage Input-Source Reverse Clamp Voltage Zero Input Voltage Drain Current (Vin = 0) Supply Current from Input Pin Test Conditions ID = 18 A; Vin = 0 ID = 2 mA; Vin = 0 Iin = -1 mA VDS = 13 V; Vin = 0 VDS = 25 V; Vin = 0 VDS = 0 V; Vin = 10 V 250 Min. 36 35 -1 -0.3 50 200 500 Typ. 42 Max. 48 Unit V V V A A A
Table 6. On (1)
Symbol VIN(th) RDS(on) Parameter Input Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = Vin; ID + Iin = 1 mA Vin = 10 V; ID = 25 A Vin = 5 V; ID = 25 A Min. 0.8 Typ. Max. 3
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5%
Table 7. Dynamic
Symbol gfs (2) Coss Parameter Forward Transconductance Output Capacitance Test Conditions VDS = 13 V; ID = 25 A
VDS = 13 V; f = 1 MHz; Vin = 0
Note: 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5%.
Table 8. Switching (3)
Symbol td(on) tr td(off) tf td(on) Parameter Turn-on Delay Time Rise Time
Turn-off Delay Time
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td(off) tf Qi
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Fall Time
Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Turn-on Current Slope Total Input Charge
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Unit
Min.
Max.
Unit
3000
pF
Min.
Typ. 100 400 800 500
Max. 200 700 1500 900 3 5 25 15
Unit ns ns ns ns s s s s A/s nC
VDD = 15 V; Id = 25 A;
Vgen = 10V; Rgen = 10 (see Figure 27)
VDD = 15 V; Id = 25 A; Vgen = 10V; Rgen = 1000 (see Figure 27)
1.8 3 18 10
(di/dt)on
VDD = 15 V; ID = 25 A Vin = 10 V; Rgen = 10 VDD = 15 V; ID = 25 A; Vin = 10 V
55 190
Note: 3. Parameters guaranteed by design/characterization.
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ELECTRICAL CHARACTERISTICS (cont'd) Table 9. Source Drain Diode
Symbol VSD(4) trr(5) Qrr(5) IRRM(5) Parameter Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions ISD = 25 A; Vin = 0 ISD = 25 A; di/dt = 100 A/s VDD = 30 V; Tj = 25 C (see test circuit, Figure 29) 800 5 15 Min. Typ. Max. 1.6 Unit V ns C A
Note: 4. Pulsed: Pulse duration = 300 s, duty cycle 1.5% 5. Parameters guaranteed by design/characterization.
Table 10. Protection
Symbol Ilim tdlim(6) Tjsh(6) Tjrs(6) Igf(6) Eas(6) Parameter Drain Current Limit Step Response Current Limit Overtemperature Shutdown Overtemperature Reset Fault Sink Current Single Pulse Avalanche Energy Vin = 10 V; VDS = 13 V Vin = 5 V; VDS = 13 V starting Tj = 25 C; VDD = 20 V Vin = 10 V; Rgen = 1 K; L = 10 mH Test Conditions Vin = 10 V; VDS = 13 V Vin = 5 V; VDS = 13 V Vin = 10 V Vin = 5 V 150 135 Min. 35 35 Typ. 50 50 50 130 Max. 65 65 Unit A A
80 200
Note: 6. Parameters guaranteed by design/characterization.
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PROTECTION FEATURES During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user's standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry. The device integrates: - OVERVOLTAGE CLAMP PROTECTION: internally set at 42V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. - LINEAR CURRENT LIMITER CIRCUIT: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh.
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- OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 170C. The device is automatically restarted when the chip temperature falls below 155C. - STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 . The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)).
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Figure 3. Thermal Impedance Figure 4. Derating Curve
Figure 5. Output Characteristics
Figure 6. Transconductance
Figure 7. Static Drain-Source On Resistance vs Input Voltage
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Figure 8. Static Drain-Source On Resistance
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Figure 9. Static Drain-Source On Resistance Figure 10. Input Charge vs Input Voltage
Figure 11. Capacitance Variations
Figure 12. Normalized Input Threshold Voltage vs Temperature
Figure 13. Normalized On Resistance vs Temperature
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Figure 14. Normalized On Resistance vs Temperature
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Figure 15. Turn-on Current Slope Figure 16. Turn-on Current Slope
Figure 17. Turn-off Drain-Source Voltage Slope
Figure 18. Turn-off Drain-Source Voltage Slope
Figure 19. Switching Time Resistive Load
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Figure 20. Switching Time Resistive Load
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Figure 21. Switching Time Resistive Load Figure 22. Current Limit vs Junction Temperature
Figure 23. Step Response Current Limit
Figure 24. Source Drain Diode Forward Characteristics
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Figure 25. Unclamped Inductive Load Test Circuits Figure 26. Unclamped Inductive Waveforms
Figure 27. Switching Times Test Circuits For Resistive Load
Figure 28. Input Charge Test Circuit
Figure 29. Test Circuit For Inductive Load Switching And Diode Recovery Times
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Figure 30. Waveforms
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PACKAGE MECHANICAL Table 11. TO-247 Mechanical Data
Symbol A A1 b b1 b2 c D E e L L1 L2 P R S Package Weight 3.55 4.50 5.50 14.20 3.70 18.50 millimeters Min 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.80 Typ Max 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75
Gr. 4.43
Figure 31. TO-247 Package Dimensions
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3.65 5.50
P025P
Note: Drawing is not to scale.
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REVISION HISTORY Table 12. Revision History
Date February-1998 18-June-2004 Revision 1 2 First Issue Stylesheet update. No content change. Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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